module output_select(
                input   wire            oclk,
                input   wire    [7:0]   RVport_mode,
                input   wire    [7:0]   unit_type,
                input   wire            port_20_en,
                input   wire            port_24_en,
                input   wire    [7:0]   SR_set,
                input   wire            display_sync,
                input   wire            vs_a,
                input   wire            o_sclk,                
                input   wire            o_load,
                input   wire            o_loeb,
                input   wire    [71:0]  o_data,
                input   wire    [4:0]   o_h_sel,
                input   wire            o_hoeb,
                output  reg     [79:0]  out,
                output  wire    [7:0]   tout
                );

wire            RV_2,RV_7,RV2_26pin;            
reg             out_40_temp,out_79_temp;

assign  RV_2=(RVport_mode[3:0]==1)?      1:0;
assign  RV_7=(RVport_mode[3:0]==2)?      1:0;
assign  RV2_26pin=(RV_2==1 && (RVport_mode[7:4]==1||unit_type[4]==1))? 1:0; 

always@*
        if(RVport_mode[7:4]==1) begin
                out_40_temp=o_h_sel[2];
                out_79_temp=o_h_sel[3];
                end
        else if(RVport_mode[7:4]==0) begin
                out_40_temp=o_h_sel[0];
                out_79_temp=o_h_sel[1];                               
                end
        
always@(posedge oclk)
begin             
        if(RV_7==1 && port_24_en==0) begin                
                out[6:0]<={o_h_sel[3:0],o_load,o_sclk,o_loeb};
                out[46:40]<={o_h_sel[3:2],o_h_sel[3:2],o_h_sel[3:2],o_h_sel[0]};
                end
        else if(RV_7==1 && port_24_en==1) begin 
                out[6:0]<={o_data[1:0],o_h_sel[1:0],o_load,o_sclk,o_loeb};
                out[46:40]<={o_data[19:18],o_data[37:36],o_data[55:54],out_40_temp};
                end
        else begin       
                out[6:0]<={o_h_sel[3:0],o_load,o_sclk,o_loeb};
                out[46:40]<={o_h_sel[3:0],o_load,o_sclk,o_loeb};
        end
end

always@(posedge oclk)
begin
        if(RV_7==1 && port_20_en==1) begin        
                out[10:7] <={o_data[2:0],o_h_sel[4]};
                out[14:12]<=o_data[6:4];  
                out[18:16]<=o_data[10:8]; 
                out[22:20]<=o_data[14:12];
                out[26:24]<=o_data[17:15];
                out[30:28]<=o_data[21:19];
                out[34:32]<=o_data[25:23];
                out[38:36]<=o_data[29:27];        
                out[50:48]<=o_data[38:36];
                out[54:52]<=o_data[42:40];
                out[58:56]<=o_data[46:44];
                out[62:60]<=o_data[50:48];
                out[66:64]<=o_data[53:51];
                out[70:68]<=o_data[57:55];
                out[74:72]<=o_data[61:59];
                out[78:76]<=o_data[65:63];
                end            
        else if(RV_7==1 && port_24_en==1) begin
                out[10:7] <=o_data[5:2];
                out[14:12]<=o_data[9:7];  
                out[18:16]<=o_data[13:11]; 
                out[22:20]<=o_data[17:15];
                out[26:24]<=o_data[23:21];
                out[30:28]<=o_data[27:25];
                out[34:32]<=o_data[31:29];
                out[38:36]<=o_data[35:33];        
                out[50:48]<=o_data[41:39];
                out[54:52]<=o_data[45:43];
                out[58:56]<=o_data[49:47];
                out[62:60]<=o_data[53:51];
                out[66:64]<=o_data[59:57];
                out[70:68]<=o_data[63:61];
                out[74:72]<=o_data[67:65];
                out[78:76]<=o_data[71:69];
                end     
        else begin
                out[10:7] <=o_data[3:0];  
                out[14:12]<=o_data[7:5];  
                out[18:16]<=o_data[11:9]; 
                out[22:20]<=o_data[15:13];
                out[26:24]<=o_data[19:17];
                out[30:28]<=o_data[23:21];
                out[34:32]<=o_data[27:25];
                out[38:36]<=o_data[31:29];        
                out[50:48]<=o_data[39:37];
                out[54:52]<=o_data[43:41];
                out[58:56]<=o_data[47:45];
                out[62:60]<=o_data[51:49];
                out[66:64]<=o_data[55:53];
                out[70:68]<=o_data[59:57];
                out[74:72]<=o_data[63:61];
                out[78:76]<=o_data[67:65];
        end        
end

always@(posedge oclk)
        if(RV2_26pin==1) begin
                out[11]<=o_data[1]; 
                out[15]<=o_data[2]; 
                out[19]<=o_data[3];
                out[23]<=o_data[4];
                out[27]<=o_data[5];
                out[31]<=o_data[6];
                out[35]<=o_data[7];
                out[47]<=o_data[8]; 
                out[51]<=o_data[9]; 
                out[55]<=o_data[10];
                out[59]<=o_data[11];
                out[63]<=o_data[12];
                out[67]<=o_data[13];
                out[71]<=o_data[14]; 
                out[75]<=o_data[15];               
                end      
        else if(RV_7==1 && port_20_en==1) begin
                out[11]<=o_data[3];  
                out[15]<=o_data[7];  
                out[19]<=o_data[11];
                out[23]<=o_h_sel[4];
                out[27]<=o_data[18];
                out[31]<=o_data[22];
                out[35]<=o_data[26];
                out[47]<=o_h_sel[4];
                out[51]<=o_data[39];
                out[55]<=o_data[43];
                out[59]<=o_data[47];
                out[63]<=o_h_sel[4];
                out[67]<=o_data[54];
                out[71]<=o_data[58]; 
                out[75]<=o_data[62];                 
                end      
        else if(RV_7==1 && port_24_en==1) begin
                out[11]<=o_data[6];  
                out[15]<=o_data[10];  
                out[19]<=o_data[14];
                out[23]<=o_data[20];
                out[27]<=o_data[24];
                out[31]<=o_data[28];
                out[35]<=o_data[32];
                out[47]<=o_data[38];
                out[51]<=o_data[42];
                out[55]<=o_data[46];
                out[59]<=o_data[50];
                out[63]<=o_data[56];
                out[67]<=o_data[60];
                out[71]<=o_data[64]; 
                out[75]<=o_data[68];                 
                end
        else begin
                out[11]<=o_data[4];  
                out[15]<=o_data[8];  
                out[19]<=o_data[12];
                out[23]<=o_data[16];
                out[27]<=o_data[20];
                out[31]<=o_data[24];
                out[35]<=o_data[28];
                out[47]<=o_data[36];
                out[51]<=o_data[40];
                out[55]<=o_data[44];
                out[59]<=o_data[48];
                out[63]<=o_data[52];
                out[67]<=o_data[56];
                out[71]<=o_data[60]; 
                out[75]<=o_data[64];                
                end
                

always @(posedge oclk)
        case(SR_set[3:0])
                4'h1:      out[39]<=o_h_sel[4];
                4'h2:      out[39]<=o_hoeb;
                4'h3:      out[39]<=~o_hoeb;
                4'hE:      out[39]<=display_sync;
                4'hF:      out[39]<=vs_a;
                default:out[39]<=0;
        endcase                                 


always @(posedge oclk)
        if(RV_7==1)
                out[79]<=out_79_temp;
        else begin
                case(SR_set[7:4])
                        4'h1:      out[79]<=o_h_sel[4];
                        4'h2:      out[79]<=o_hoeb;
                        4'h3:      out[79]<=~o_hoeb;
                        4'hE:      out[79]<=display_sync;
                        4'hF:      out[79]<=vs_a;
                        default:out[79]<=0;
                endcase
        end
        
assign tout={RV_7};        
endmodule